Current Projects:
- PIT Suite: Instruction Trace Profiling Tool for Microarchitecture Exploration. Open source!
- LLMFlux: A framework for batch LLM inference and interactive model serving on Slurm-managed HPC systems. Open source!
- OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design. GitHub | Hugging Face dataset.
- Naviq: A gem5-based simulator for cycle-level modeling of AMD Network-on-Chip (NoC) architectures. Open source!
- MAAC: Multi-Accelerator Architecture and Communication Co-design for Accelerating Graph Neural Networks. Open source!
- HeteroMosaic: A scheduling framework for heterogeneous accelerators on AMD Ryzen AI SoCs. Open source!
- TileFuse: A mixed-precision kernel library for W4A16 and W8A16 LLM inference on AMD NPUs. Open source!
- GREEN: Scalable, energy-efficient cloud workload scheduling and placement using graph neural networks and reinforcement learning. Open source!
- HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing. Open source!
- SemanticXR: Low-power, real-time semantic mapping and querying with a device-cloud architecture. Open source!
- Boba: Batched Simulation for Physics-Based Gaussian Digital Twins. Open source!
- X-MoE: A cross-platform framework for scalable training of Mixture-of-Experts models on GPU systems. Open source!
- MegaFold: Efficient Training of Next-Generation 3D Attention Protein Models on Cross-Platform GPUs. Open source!
- Universal Checkpointing (UCP): Flexible and efficient checkpointing for large-scale distributed training with reconfigurable parallelism, implemented in DeepSpeed. Open source!
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ILLIXR (ILLInois eXtended Reality) testbed: here
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ArchGen: A Graph-to-Silicon Hardware Generation Framework for Design Space Exploration. Open source!
- Chrysalis-HLS: An Iteratively-refined Dataset for High-Level Synthesis Functional Verification through LLM-Aided Bug Injection. Open source!
- SnapKV: LLM Knows What You are Looking for Before Generation. Open source!
- Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads. Open source!
- OS4C: An Open-Source SR-IOV System for SmartNIC-based Cloud Platforms. Open source!
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TiNA: Tiered network buffer architecture for fast networking in chiplet-based CPUs. Open source!
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NetZIP: algorithm/hardware co-design of in-network lossless compression for distributed large model. Open source!
- HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis. Open source!
- ScaleHLS: A Scalable High-Level Synthesis Framework on top of MLIR. Open source!
- PyLog: A Python to FPGA Compiler. Open source!
- FSSD: FPGA-based SSD Emulator for SSDs
- NimBlock: Scheduling for Virtualized FPGA and Versal Devices. Open source!
- Qilin: FPGA-based Shared Virtual Memory System
- Morpheus: A Polymorphous Design for General-purpose Code Acceleration
- SmartNIC: Evaluating SmartNIC performance in the Cloud
- Urbana Project: A New Open-Source Educational FPGA board