Publications

  • Hanchen Ye, Hyegang Jun, and Deming Chen, “HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis”, Proceedings of ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024.
  • Yizhen Lu, Curtis Yu, and Deming Chen, “SSDe: FPGA-based SSD Express Emulation Framework,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, October 2023.
  • Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seung Won Min, Wen-Mei Hwu, and Deming Chen, “FSSD: FPGA-based Emulator for SSDs,” Proceedings of the International Conference on Field-Programmable Logic and Applications, September 2023.
  • Deming Chen, “Lightning Talk: The Next Wave of High-level Synthesis,” Proceedings of ACM/IEEE Design Automation Conference, July 2023. (Invited)
  • Dong Kai Wang, Jiaqi Lou, Naiyin Jin, Edwin Mascarenhas, Rohan Mahapatra, Sean Kinzer, Soroush Ghodrati, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, and Nam Sung Kim. MESA: Microarchitecture Extensions for Spatial Architecture Generation. Proceedings of the Annual International Symposium on Computer Architecture (ISCA), June 2023.
  • Meghna Mandava, Paul Reckamp, and Deming Chen, “Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization,” Proceedings of International Symposium on Computer Architecture (ISCA), June 2023.
  • Hanchen Ye, Hyegang Jun, Jin Yang, and Deming Chen “High-level Synthesis for Domain Specific Computing,” Proceedings of International Symposium on Physical Design, March 2023. (Invited)
  • Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, and Peipei Zhou, “CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture,” Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2023.
  • Meghna Mandava and Deming Chen, “Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization,” Poster, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2023.
  • Hyegang Jun, Hanchen Ye, Hyunmin Jeong, and Deming Chen, “AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis,” ACM Transactions on Reconfigurable Technology and Systems, 2022. To appear.
  • Jianwei Zheng, Yu Liu, Xuejiao Liu, Luhong Liang, Deming Chen, and Kwang-Ting Cheng, “ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design,” IEEE Transactions on Computers, 2022. To appear. (Featured story at IEEE Spectrum: Deep Learning Gets a Boost From New Reconfigurable Processor)
  • Xinyu Chen, Feng Cheng, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen, “ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS,” ACM Transactions on Reconfigurable Technology and Systems, 2022. To appear.
  • Vibhakar Vemulapati and Deming Chen, “FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs,” Proceedings of IEEE International Conference on Field Programmable Technology, December 2022.
  • Edward Richter and Deming Chen, “Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2022.
  • Hanchen Ye, Gregory Jun, Hyunmin Jeong, Stephen Neuendorffer, and Deming Chen, “Invited: ScaleHLS, a Scalable High-level Synthesis Framework with Multi-level Transformations and Optimizations,” Proceedings of IEEE/ACM Design Automation Conference, July 2022. (Invited)
  • Ashutosh Dhar, Edward Richter, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, and Deming Chen, “DML: Dynamic Partial Reconfiguration with Scalable Task Scheduling for Multi-Applications on FPGAs”, IEEE Transactions on Computers, Volume: 71, Issue: 10, Page(s): 2577 – 2591, October 2022.
  • Xiaofan Zhang, Yuhong Li, Junhao Pan, and Deming Chen, “Algorithm/Accelerator Co-Design and Co-Search for Edge AI”, IEEE Transactions on Circuits and Systems II, Volume: 69, Issue: 7, Page(s): 3064 – 3070, July 2022.
  • Xiaofan Zhang, Yuan Ma, Jinjun Xiong, Wen-mei Hwu, Volodymyr Kindratenko, and Deming Chen, “Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems”, Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 41, Issue: 6, Page(s): 1606 – 1619, June 2022.
  • Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, and Deming Chen, “ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation,” Proceedings of IEEE International Symposium on High-Performance Computer Architecture, April 2022.
  • Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, and Deming Chen, “HiKonv: High Throughput Quantized Convolution with Novel Bit-wise Management and Computation”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2022.
  • Sitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, and Wen-Mei Hwu, “PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow,” IEEE Transactions on Computers, Vol. 70, No. 12, December 2021.
  • Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, and Deming Chen, “A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems,” Proceedings of the Workshop for Programming Environments for Heterogeneous Computing (co-located with SC21), November 2021.
  • Mang Yu, Sitao Huang, and Deming Chen, “Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis”, Proceedings of International Conference on Intelligent Data Engineering and Automated Learning, November 2021. (Best Paper Award)
  • Seung Won Min, Kun Wu, Sitao Huang, Mert Hidayetoğlu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, and Wen-mei Hwu, “Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture”, Proceedings of VLDB Endowment (PVLDB), Volume 14, Issue 11, July 2021.
  • Hyunmin Jeong and Deming Chen, “TwinDNN: A Tale of Two Deep Neural Networks”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2021.
  • Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-mei Hwu, and Deming Chen, “Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications”, Proceedings of International Symposium on Applied Reconfigurable Computing, June 2021.
  • Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen, “ThunderGP: HLS-based Graph Processing Framework on FPGAs”, Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2021. DOI: https://dl.acm.org/doi/10.1145/3431920.3439290
  • Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen and Zhiru Zhang, “FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations,” Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2021. (Best Paper Candidate). DOI: https://dl.acm.org/doi/10.1145/3431920.3439296
  • Junhao Pan and Deming Chen, “Accelerate Non-unit Stride Convolutions with Winograd Algorithms”, Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2021. DOI: https://dl.acm.org/doi/10.1145/3394885.3431534
  • Seung Won Min, Vikram Sharma Mailthody, Zaid Qureshi, Jinjun Xiong, Eiman Ebrahimi, and Wen-mei Hwu. 2020. EMOGI: efficient memory-access for out-of-memory graph-traversal in GPUs. Proc. VLDB Endow. 14, 2 (October 2020), 114–127. DOI:https://doi.org/10.14778/3425879.3425883
  • Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong, Jian Huang, Wen–mei Hwu, Nam Sung Kim, Deming Chen, “FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache,” 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, 2020, pp. 102-117, doi: 10.1109/MICRO50266.2020.00021.
  • Subho S. Banerjee, Saurabh Jha, Zbigniew T. Kalbarczyk, and Ravishankar K. Iyer. “Inductive-bias-driven Reinforcement Learning for Efficient Schedules in Heterogeneous Clusters.”  Proceedings of the 37th International Conference on Machine Learning, Online, PMLR 119, 2020. (https://arxiv.org/abs/1909.02119)
  • Subho S. Banerjee, Zbigniew T. Kalbarczyk, and Ravishankar K. Iyer. 2019. AcMC²: Accelerating Markov Chain Monte Carlo Algorithms for Probabilistic Models. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS ’19). Association for Computing Machinery, New York, NY, USA, 515–528. DOI:https://doi.org/10.1145/3297858.3304019